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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad8322 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2000 5 v catv line driver coarse step output power control functional block diagram decode shift register data latch ad8322 v in+ v in v out+ v out buffer r1 r2 attenuation core 8 8 8 power-down logic power amp pd gnd (12 pins) daten data clk z in (single) = 210 z in (diff) = 235 z out diff = 75 v cc (7 pins) diff or single input amp features supports docsis standard for reverse path transmission gain programmable in 6 db steps over a 42 db range low distortion at 60 dbmv output C58 dbc sfdr at 21 mhz C56 dbc sfdr at 42 mhz output noise level C46 dbmv in 160 khz bandwidth maintains 75 output impedance power-up and power-down condition 180 mhz bandwidth 5 v supply operation supports spi interfaces applications gain programmable line driver docsis-compliant data modems interactive set-top boxes pc plug-in modems general-purpose digitally controlled variable gain block general description the ad8322 is a low-cost, digitally controlled variable gain ampli- fier optimized for coaxial line driving applications such as cable modems that are designed to the mcns-docsis upstream standard. an 8-bit serial word determines the desired output gain over a 42.14 db range, with gain steps of 6.02 db/major carry. the ad8322 comprises a digitally controlled variable attenuator of 0 db to ?2.14 db, which is preceded by a low-noise, fixed-gain buffer and is followed by a low-distortion, high-power ampli- fier. the ad 8322 accepts a differential or single-ended input signal. the output is specified for driving a 75 ? load, such as coaxial cable. distortion performance of ?8 dbc is achieved with an output level up to 60 dbmv at 21 mhz bandwidth. a key performance and cost advantage of the ad8322 results from the ability to maintain a constant 75 ? output impedance during power-up and power- down conditions. this eliminates the need for external 75 ? termination resulting in twice the effective output voltage when compared to a standard operational amplifier. the ad8322 is packaged in a low-cost 28-lead tssop, oper ates from a single 5 v supply, and has an operatio nal temperature range of ?0 c to +85 c. gain code decimal 1 55 distortion dbc 60 65 70 75 2 4 8 16 32 64 128 f o = 42mhz v o = 60dbmv @ max gain hd3 hd2 figure 1. harmonic distortion vs. gain control obsolete
rev. 0 C2C ad8322?pecifications (t a = 25 c, v s = 5 v, r l = r in = 75 , v in = 92 mv p-p differential, v out measured through a 1:1 transformer 1 with insertion loss of 0.5 db @ 10 mhz unless otherwise noted) parameter conditions min typ max unit input characteristics specified ac voltage p out = 60 dbmv, max gain 92 mv p-p noise figure max gain, f = 10 mhz 11.8 db input resistance single-ended input 210 ? differential input 235 ? input capacitance 2pf gain control interface gain range 41.0 42.14 43.2 db maximum gain gain code = 1xxxxxxx 27.5 29.5 31.5 db minimum gain gain code = 00000001 ?4.64 ?2.64 ?0.64 db gain scaling factor 6.02 db/major carry output characteristics bandwidth (? db) all gain codes 180 mhz bandwidth roll-off f = 65 mhz 0.25 db bandwidth peaking f = 65 mhz 0.05 db output noise max gain, f = 10 mhz ?2 dbmv in 160 khz bw min gain, f = 10 mhz ?6 dbmv in 160 khz bw power-down mode, f = 10 mhz ?8 dbmv in 160 khz bw 1 db compression point max gain, f = 10 mhz 19 dbm differential output impedance power-up and power-down 75 20% ? overall performance second order harmonic distortion 2 f = 5 mhz, p out = 60 dbmv @ max gain 64 dbc f = 14 mhz, p out = 60 dbmv @ max gain 60 dbc f = 21 mhz, p out = 60 dbmv @ max gain 58 dbc f = 32 mhz, p out = 60 dbmv @ max gain 57 dbc f = 42 mhz, p out = 60 dbmv @ max gain 56 dbc f = 65 mhz, p out = 60 dbmv @ max gain 52 dbc third order harmonic distortion f = 5 mhz, p out = 60 dbmv @ max gain 67 dbc f = 14 mhz, p out = 60 dbmv @ max gain 64 dbc f = 21 mhz, p out = 60 dbmv @ max gain 61 dbc f = 32 mhz, p out = 60 dbmv @ max gain 58 dbc f = 42 mhz, p out = 60 dbmv @ max gain 56 dbc f = 65 mhz, p out = 60 dbmv @ max gain 53 dbc gain linearity error f = 10 mhz, code to code 0.2 db output settling to 1 mv due to gain change min to max gain 60 ns due to input change max gain, v in = 0 v to 0.09 v p-p 30 ns signal feedthrough max gain, power-down, f = 42 mhz, ?4 dbc v in = 0.09 v p-p power control power-up settling time to 1 mv max gain, v in = 0 300 ns power-down settling time to 1 mv max gain, v in = 0 40 ns between burst transients 3 equivalent p out = 17.6 to 35.67 dbmv 3 mv p-p equivalent p out = 60 dbmv 16 mv p-p power supply operating range 4.75 5 5.25 v quiescent current power-up mode 100 113 126 ma power-down mode 44 54 60 ma operating temperature ?0 +85 c range notes 1 toko # 617 db-a0070 used for above specifications. macom etc-1-it-15 can be substituted. 2 all distortion measurements taken with differential input signal and represent worst distortion across all gain codes. 3 between burst transients measured at the output of pulse b5008 42 mhz diplexer. specifications subject to change without notice. obsolete
rev. 0 ad8322 C3C logic inputs (ttl/cmos compatible logic) parameter min typ max unit logic ??voltage 2.1 5.0 v logic ??voltage 0 0.8 v logic ??current (v inh = 5 v) clk, sdata, daten 020na logic ??current (v inl = 0 v) clk, sdata, daten ?00 ?00 na logic ??current (v inh = 5 v) pd 50 190 a logic ??current (v inl = 0 v) pd ?50 ?0 a timing requirements parameter min typ max unit clock pulsewidth (t wh ) 16.0 ns clock period (t c ) 32.0 ns setup time sdata vs. clock (t ds ) 5.0 ns setup time daten vs. clock (t es ) 15.0 ns hold time sdata vs. clock (t dh ) 5.0 ns hold time daten vs. clock (t eh ) 3.0 ns input rise and fall times, sdata, daten , clock (t r , t f )1 0 n s (full temperature range, v cc = 5 v, t r = t f = 4 ns, f clk = 8 mhz unless otherwise noted.) ( daten , clk, sdata, pd , v cc = 5 v: full temperature range) t es valid data word g1 msb. . . .lsb gain transfer (g1) t ds t eh 8 clock cycles gain transfer (g2) t off t gs analog output signal amplitude (p-p) pd pedestal clk sdata daten t on t c t wh valid data word g2 figure 2. serial interface timing valid data bit msb msb-1 msb-2 t ds t dh sdata clk figure 3. sdata timing table i. gain vs. gain code decimal 8-bit spi data word gain code msb lsb nominal gain (db) 1 00000001 ?2.64 2 00000010 ?.62 4 00000100 ?.60 8 00001000 5.42 16 00010000 11.44 32 00100000 17.46 64 01000000 23.48 128 1xxxxxxx 29.50 0 = low, 1 = high, x = don? care. obsolete
rev. 0 ad8322 C4C ordering guide model temperature range package description ja package option ad8322aru ?0 c to +85 c 28-lead tssop 67.7 c/w * ru-28 ad8322aru-reel 40 c to +85 c 28-lead tssop 67.7 c/w * ru-28 ad8322-eval evaluation board * thermal resistance measured on semi standard 4-layer board. absolute maximum ratings * supply voltage +v s pins 6, 8, 9, 20, 21, 23, 27 . . . . . . . . . . . . . . . . . . . . . . . 6 v input voltages pins 25, 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 v pins 1, 2, 3, 7 . . . . . . . . . . . . . . . . . . . . . . . ?.8 v to +5.5 v internal power dissipation tssop (ru) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.90 w operating temperature range . . . . . . . . . . . ?0 c to +85 c storage temperature range . . . . . . . . . . . . ?5 c to +150 c lead temperature, soldering 60 seconds . . . . . . . . . . . 300 c * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. pin configuration top view (not to scale) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ad8322 daten gnd sdata vcc clk vin gnd vin+ vcc gnd pd vcc gnd gnd gnd vcc vcc vcc vcc gnd gnd gnd gnd gnd gnd out out+ byp caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad8322 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device pin function descriptions pin no. mnemonic description 1 sdata serial data input. this digital input allows for an 8-bit serial (gain) word to be loaded into the internal register with the msb (most significant bit) first. 2 clk clock input. the clock port controls the serial attenuator data transfer rate to the 8-bit master-slave register. a logic 0-to-1 transition latches the data bit and a 1-to-0 transfers the data bit to the slave. this requires the input serial data word to be valid at or before this clock transition. 3 data enable low input. this port controls the 8-bit parallel data latch and shift register. a logic 0- to-1 transition transfers the latched data to the attenuator core (updates the gain) and simultaneously inhibits serial data transfer into the register. a 1-to-0 transition inhibits the data latch (holds the previous gain state) and simultaneously enables the register for serial data load. 4, 11, 12, 13, gnd common external ground reference. 14, 15, 16, 17, 18, 22, 24, 28 5 byp internal bypass. this pin must be externally ac-decoupled (0.1 f capacitor). 6, 8, 9, 20, vcc common positive external supply voltage. a 0.1 f capacitor must decouple each pin. 21, 23, 27 7 logic ??powers down the part. logic ??powers up the part. 10 out negative output signal. 19 out+ positive output signal. 25 vin+ noninverting input. dc-biased to approximately v cc /2. refer to applications section for proper termination. 26 vin i nverting input. dc-biased to approximately v cc /2. refer to applications section for proper termination. obsolete
rev. 0 ad8322 C5C typical performance characteristics gain control decimal 1 0.15 gain error db 2 4 8 16 32 64 128 0.10 0.05 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 f = 5mhz f = 10mhz f = 42mhz f = 65mhz tpc 2. gain error vs. gain control frequency mhz 36 11 k gain db 100 10 30 24 18 12 6 0 6 12 18 gc64 gc32 gc16 gc8 gc4 gc2 gc1 gc128 tpc 3. ac response vs. gain con trol v in+ v in v cc gnd out ad8322 byp out+ 0.1f 0.1f 1:1 toko 617db-a0070 c l 0.1f 0.1f 432 75 75 75 + v o 5v 10f 0.1f +1/2 v in 1/2 v in 0.1f device under test tpc 1. test circuit frequency mhz 32 1 100 10 gain db 30 28 26 24 p o = 60dbmv @ max gain c l = 0pf c l = 10pf c l = 20pf c l = 50pf tpc 4. ac response for various cap acitor loads gain code decimal 1 32 output noise dbmv in 160 khz bw 2 4 8 16 32 64 128 36 40 44 48 f = 10mhz pd = 1 tpc 5. output noise vs. gain code obsolete
rev. 0 ad8322 C6C frequency mhz 0 11k feedthrough dbc 100 10 10 20 30 40 50 60 70 80 90 100 max gain min gain gain code 0 pd = 0 tpc 6. input signal feedthrough vs. frequency fundamental frequency mhz 45 5 65 distortion dbc 50 55 60 65 55 45 35 25 15 p o = 58dbmv at max gain p o = 62dbmv at max gain p o = 60dbmv at max gain tpc 7. second order harmonic distortion vs. frequency for vari ous output levels fundamental frequency mhz 45 5 65 distortion dbc 50 60 70 75 55 45 35 25 15 55 65 p o = 62dbmv at max gain p o = 58dbmv at max gain p o = 60dbmv at max gain tpc 8. third order harmonic distortion vs. frequency for vari ous output levels frequency mhz 11k impedance 100 10 170 150 130 110 90 70 50 30 170 pd = 1 pd = 0 tpc 9. input impedance vs. fre quency (inputs shunted with 432 ? ) frequency mhz 150 0.1 impedance 125 100 75 50 25 1 10 100 1k pd = 1 pd = 0 tpc 10. output impedance vs. frequency obsolete
rev. 0 ad8322 C7C applications general application the ad8322 is primarily intended for use as the upstream power amplifier (pa) in docsis (data over cable service interface specifications) certified cable modems and catv set- top boxes. upstream data is modulated in qpsk or qam format. this is done with dsp or a dedicated qpsk/qam modulator. the amplifier receives its input signal from the qpsk/qam modula- tor or from a dac. in either case the signal must be low-pass filtered before being applied to the amplifier. because the dis tance from the cable modem to the central office will vary with each subscriber, the ad8322 must be capable of varying its output power by applying gain or attenuation to ensure that all signals arriving at the central office are of the same amplitude. the upstream signal path contains components such as a transformer and diplexer that will result in some amount of power loss. there- fore, the ampli fier must be capable of providing enough power into a 75 ? load to overcome these losses without sacrificing the integrity of the output signal. operational description the ad8322 is composed of three analog functions in the power- up or forward mode. the input amplifier (preamp) can be used single-ended or differentially. if the input is used in the differen- tial configuration, it is imperative that the input signals be 180 degrees out of phase and of equal amplitudes. this will ensure the proper gain accuracy and harmonic performance. the preamp stage drives a dac, which provides the bulk of the ad8322? attenuation (7 bits or 42.14 db). the signals in the preamp and dac gain blocks are differential to improve the psrr and linear- ity. a differential current is fed from the dac into the output stage, which amplifies these currents to the appropriate levels neces sary to drive a 75 ? load. the output stage utilizes negative feedback to implement a differential 75 ? output impedance. this elimi nates the need for external m atching resistors. spi programming and gain adjustment gain programming of the ad8322 is accomplished using a serial peripheral interface (spi) and three digital control lines, daten , sdata, and clk. to change the gain, eight bits of data are streamed into the serial shift register through the sdata port. the sdata load sequence begins with a falling edge on the daten pin, thus activating the clk line. although the clk line is now activated, no change in gain is observed. with the clk line activated, data on the sdata line is clocked into the serial shift register, most significant bit (msb) first, on the rising edge of each clk pulse. a rising edge on the daten line latches the contents of the shift register into the attenuator core resulting in a well-controlled change in the output signal level. the serial interface timing for the ad8322 is shown in fig- ures 2 and 3. the programmable gain range of the ad8322 is ?2.64 db to +29.5 db and scales 6.02 db for each major carry. because the ad8322 was characterized with a toko trans former, the stated gain values already t ake into account the losses asso- ciated with the transformer. valid gain codes are the major carries from decimal 1?28 (decimal values 1, 2, 4, 8, 16, 32, 64, 128). the resulting gain for each code can be seen in table i. alth ough the ad8322 is designed for use with the previous eight codes, the intermediate codes can be used. the gain transfer function is as follows: a v = 20 log (0.2332 code) for 1 code 128 a v = 29.5 db for code 128 where a v is the gain in db and code is the decimal equivalent of the 8-bit word. figure 4 shows the gain characteristic for all possible values (except 0) in an 8-bit word. code 0 may be used if more feedthrough isolation is required. it typically provides ?5 db of isolation across the 5 mhz to 65 mhz upstream band. gain code decimal 35 0 gain db 30 25 20 15 10 0 5 10 15 20 32 64 96 128 160 192 224 256 5 figure 4. gain vs. gain code input bias, impedance, and termination the v in+ and v in inputs have a dc bias level of approxim ately v cc /2, therefore the input signal should be ac-coupled. the differential input impedance is approximately 235 ? while the single-ended input impedance is 210 ? . if the ad8322 is being operated in a single-ended input configuration with a desired input impedance of 75 ? , the v in+ and v in inputs should be terminated as shown in figure 5. for input impedances other than 75 ? , the value of r1 in figure 5 can be calculated using the following equation: zr in = 1 210 z in = 75 ad8322 r1 = 118 figure 5. single-ended input termination obsolete
rev. 0 ad8322 C8C output bias, impedance, and termination the differential output pins v out+ and v out are also biased to a dc level of approximately v cc /2. therefore, the outputs should be ac-coupled before being applied to the load. this may be accomplished by connecting 0.1 f capacitors in series with the outputs as shown in the typical applications circuit of figure 6. the differential output impedance of the ad8322 is inter nally maintained at 75 ? , regardless of whether the amplifier is in forward transmit mode or reverse power-down mode, elimi- nating the need for external back termination resistors. a 1:1 transformer (toko #617db-a0070) is used to couple the amplifier s differential output to the coaxial cable while main- taining a proper impedance match. if the output signal is being evaluated on standard 50 ? test equipment, a 75 ? to 50 ? pad must be used to provide the test circuit with the correct impedance match. power supply decoupling, grounding, and layout consid erations careful attention to printed circuit board layout details will prevent problems due to associated board parasitics. proper rf design technique is mandatory. the 5 v supply power should be delivered to each of the vcc p ins via a low impedance power bus to ensure that each pin is at the same potential. the power bus should be decoupled to ground with a 10 f tantalum capacitor located in close proximity to the ad8322. in addition to the 10 f capacitor, each vcc pin should be individually decoupled to ground with a 0.1 f ceramic chip capacitor located as close to the pin as possible. the pin labeled byp (pin 5) should also be decoupled with a 0.1 f capacitor. the pcb should have a low impedance ground plane covering all unused portions of the component side of the board, except in the area of the input and output traces (see figure 11). it is important to connect all of the ad8322 ground pins to ensure proper grounding of all internal nodes. the differential input and output traces should be kept as short and as symmetrical as possible. in addition, the input and output traces should be kept far apart in order to minimize coupling (crosstalk) through the board. following these guidelines will improve the overall performance of the ad8322 in all applications. initial power-up when the 5 v supply is first applied to the vcc pins of the ad8322, the gain setting of the amplifier is indeterminate. therefore, as power is first applied to the amplifier, the pd pin should be held low (logic 0) thus preventing forward signal transmission. after power has been applied to the amplifier, the gain can be set to the desired level by following the procedure in the spi programming and gain adjustment section. the pd pin can then be brought from logic 0 to 1, enabling forward signal transmission at the desired gain level. asynchronous power-down the asynchronous pd pin is used to place the ad8322 into between burst mode while maintaining a differential output impedance of 75 ? . applying a logic 0 to the pd pin activates the on-chip reverse amplifier, providing a 52% reduction in con- sumed power. the supply current is reduced from approxi mately 113 ma to approximately 54 ma. in this mode of operation, between burst noise is minimized and the amplifier can no longer transmit in the upstream direction. distortion, adjacent channel power, and docsis in order to deliver 58 dbmv of high-fidelity output power required by docsis, the pa should be able to deliver about 60 to 61 dbmv in order to make up for losses associated with the transformer and diplexer. it should be noted that the ad8322 was characterized with the toko 617db-a0070 transformer. tpc 7 and tpc 8 show the ad8322 second and third harm onic distortion performance versus fundamental frequency for vari- ous output power levels. these figures are useful for determining the in-band harmonic levels from 5 mhz to 65 mhz. harm onics higher in frequency will be sharply attenuated by the low-pass filter function of the diplexer. another measure of signal integ- rity is adjacent channel power or acp. docsis section 4.2.9.1.1 states, spurious emissions from a transmitted carrier may occur sdata clk daten gnd1 byp vcc pd vcc1 vcc2 out gnd2 gnd3 gnd4 gnd5 gnd12 vcc6 vin vin+ gnd11 vcc5 gnd10 vcc4 vcc3 out+ gnd9 gnd8 gnd7 gnd6 ad8322tssop 5v pd daten sdata clk 10f 25v 0.1f 0.1f 0.1f 0.1f0 . 1 f toko 617db-a0070 to diplexer z in = 75 0.1f 0.1f 0.1f 0.1f 0.1f 432 v in v in+ z in = 150 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 27 26 25 24 23 22 21 20 19 18 17 16 15 0.1f 0.1f figure 6. typical applications circuit obsolete
rev. 0 ad8322 C9C in an adjacent channel which could be occupied by a carrier of the same or different symbol rates. figure 7 shows the mea sured acp, for a 16 qam, 60 dbmv signal, taken at the output of the ad8322 evaluation board (see figure 13 for evaluation board schematic). the transmit channel width and adjacent channel width in figure 7 correspond to symbol rates of 160 k sym/sec . table ii shows the acp results for the ad8322 for all condi tions in docsis table 4-7 adjacent channel spurious emissions. 10 20 30 40 70 50 60 80 center 10mhz 60khz span 600khz cl1 c0 c0 cu1 cl1 rbw 500hz rf att 40db vbw 5khz swt 12s unit dbm ch pwr 5.39dbm acp up 54.22db acp low 56.84db f1 cu1 figure 7. adjacent channel power table ii. acp performance for all docsis conditions (all values in dbc) transmit channel symbol rate 2560 k sym/sec 54.2 160 k sym/sec 320 k sym/sec 640 k sym/sec 1280 k sym/sec 2560 k sym/sec adjacent channel symbol rate 54.7 55.4 53.8 54.6 54.6 54.0 54.1 54.5 53.9 54.1 53.9 54.2 54.2 54.2 160 k sym/sec 320 k sym/sec 640 k sym/sec 1280 k sym/sec 56.6 55.1 54.4 54.3 53.8 55.9 54.8 54.1 53.7 53.5 noise and docsis at minimum gain, the ad8322 s output noise spectral density is 12 nv/ hz measured at 10 mhz. docsis table 4-8, spurious emissions in 5 mhz to 42 mhz specifies the output noise for various symbol rates. the calculated noise power in dbmv for 160 k sym/sec is: 20 12 160 60 46 4 2 log . nv hz khz dbmv ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? += comparing the computed noise power of 46.4 dbmv to the 8 dbmv signal yields 54.4 dbc, which meets the required level of 53 dbc set forth in docsis table 4-8. as the ad8322 s gain is increased from this minimum value, the output signal increases at a faster rate than the noise, resulting in a signal-to- noise ratio that improves with gain. in transmit disable mode the output noise spectral density computed over 160 k sym/sec is 1.0 nv/ hz or 68 dbmv. evaluation board features and operation the ad8322 evaluation board (part # ad8322-eval) and control software can be used to control the ad8322 upstream cable driver via the parallel port of a pc. a standard printer cable connected between the parallel port and the evaluation board is used to feed all the necessary data to the ad8322 by means of the windows based, microsoft visual basic control software. this package provides a means of evaluating the amplifier by provid- ing a convenient way to program the gain/attenuation as well as offering easy control of the amplifiers asynchronous pd pin. with this evaluation kit the ad8322 can be evaluated with either a single-ended or differential input configuration. the amplifier can also be evaluated with or without the pulse diplexer in the output signal path. to remove the diplexer from the signal path, move the two 0 ? chip resistors r18 and r10 to locations r11 and r20. a schematic of the evaluation board is provided in figure 13. overshoot on pc printer ports the data lines on some pc parallel printer ports have excessive overshoot that may cause communications problems when pre- sented to the clk pin of the ad8322 (tp5 on the evaluation board). the evaluation board was designed to accommodate a series resistor and shunt capacitor (r1 and c15) to filter the clk signal if required. transformer and diplexer a 1:1 transformer is needed to couple the differential outputs of the ad8322 to the cable while maintaining a proper impedance match. the specified transformer is available from toko (part # 617db-a0070), however, ma/com part # etc-1-1t-15 can also be used. the evaluation board is equipped w ith the toko transformer, but is also designed to accept the ma/com transform er. the pulse diplexer included on the evaluation board provides a high-order low-pass filter function, typically used in the upstream path. the ability of the pulse diplexer to achieve docsis compliance is neither expressed nor implied by analog devices inc. data on the diplexer should be obtained from p ulse. differential inputs the ad8322-eval evaluation board is designed to accommo- date a mini-circuits t1-6t-kk81 1:1 transformer for the purpose of converting a single-ended (ground referenced) input signal to differential inputs. figure 8 and the following paragraphs iden- tify three options for providing differential input signals to the ad8322 evaluation board. windows is a registered trademark of microsoft corporation. obsolete
rev. 0 ad8322 C10C single-ended-to-differential input (figure 8 option 1) install the mini-circuits t1-6t-kk81 1:1 transformer in the t1 location of the evaluation board. install 0 ? chip resistors in r12, r13, and r17, and leave r14, r16, and r19 open. for 75 ? input impedance, install a 110 ? resistor in r7 located on the back side of the evaluation board and leave r5 and r6 open. in this configuration the input signal must be applied to the v in+ port of the evaluation board from a single-ended 75 ? signal source. for input impedances other than 75 ? , use the following equation to compute the correct value for r7. desired input impedance = r7 235 single-ended-to-differential input (figure 8 option 2) install the mini-circuits t1-6t-kk81 1:1 transformer in the t1 location of the evaluation board. install 0 ? chip resistors in r12, r13, r17, and r19, and leave r14 and r16 open. for 75 ? input impedance, install 55 ? resistors in r5 and r6 located on the back side of the evaluation board and leave r7 open. in this configu- ration the input signal must be applied to the v in+ port of the evaluation board from a single-ended 75 ? signal source. for input impedances other than 75 ? , use the following equation to compute the correct values for r5 and r6. r5 = r6 = r, desired input impedance = 2 (r 117.5) differential input (figure 8 option 3) if a differential signal source is available, it may be applied di rectly to both the v in+ and v in input ports of the evaluation board. in this case, install 0 ? chip resistors in r8, r14, r15, and r16, and leave r12, r13, and r19 open. referring to figure 8 option 3 and the ad8322 evaluation board, a differential input impedance of 150 ? can be achieved by installing a 432 ? resistor in r7, leaving r5 and r6 open. if another input impedance is desired, the following equation can be used to compute the correct value for r7. desired input impedance = r7 235 diff in t1 ad8322 r7 option 1 differential input termination diff in t1 r5 r6 ad8322 option 2 differential input termination r7 vin+ ad8322 vin option 3 differential input termination figure 8. differential input termination options installing the visual basic control software to install the cabdrive_22 evaluation board control soft- ware, first close all windows applications and run setup.exe located on disk 1 of the ad8322 evaluation software. follow the on-screen instructions and insert disk 2 when prompted to do so. enter the path of the directory into which the software will be installed and select the button in the upper left corner to complete the installation. running the software to invoke the control software, go to start -> programs -> cabdrive_22, or select the ad8322.exe icon from the directory containing the software. controlling the gain/attenuation of the ad8322 the slide bar controls the ad8322 s gain/attenuation, which is displayed in db and in v/v. although the ad8322 is designed for use at the eight gain codes described in the spi programming and gain adjustment section, all of the intermediate codes are included in the software. code 0 is also included because of the high isolation it provides. the gain code (i.e., position of the slide bar) is displayed in decimal, binary, and hexadecimal (see figure 9). power-up and power-down the power-up and power-down buttons select the mode of operation of the ad8322 by controlling the logic level on the asynchronous pd pin. the power-up button applies a logic 1 to the pd pin putting the ad8322 in forward transmit mode. the power-down button applies a logic 0 to the pd pin select- ing reverse mode, where the forward signal transmission is disabled while a back termination of 75 ? is maintained. memory section the memory section of the software provides a convenient way to alternate between two gain settings. the x->m1 but- ton stores the current value of the gain slide bar into memory while the rm1 button recalls the stored value, returning the gain slide bar to that level. the x->m2 and rm2 buttons work in the same manner. obsolete
rev. 0 ad8322 C11C figure 9. screen display of windows-based control software obsolete
rev. 0 ad8322 C12C figure 10. evaluation boardassembly (component side) figure 11. evaluation board layout (component side) obsolete
rev. 0 ad8322 C13C figure 12. evaluation boardsolder side obsolete
rev. 0 ad8322 C14C nc = 5 t1 1:1 nc = 2 t2b 1:1 t2a dni 1:1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0.1f 0.1f 0.1f 0.1f c8 c7 c6 c5 c13 0.1f c12 0.1f r5 dni r7 118 tp14 yel tp13 yel 4 6 3 1 2 r8 0 r9 dni vin vin+ s2 s3 g1 g2 g3 g4 g5 g6 g7 g8 g9 18 17 16 15 14 13 12 11 10 pulseb5008 a ab b u2 s4 s1 tp21 dni tp22 dni 1 3 5 9 tp10 dni r4 dni r3 0 cable hpp tp9 dni tp11 dni tp12 dni c11 0.1f toko-b4f etcc1-1t 4 3 4 5 5 1 3 1 2 tp8 dni tp7 dni c10 0.1f tp4 tp6 r2 0 wht wht pd c14 dni tp2 tp5 r1 0 wht wht clk c15 dni tp17 tp19 wht tp1 wht sdata tp3 wht daten p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 amp-552742 vcc j1 j2 agnd blk tp20 c18 10f 25v tp15 red + 1 1 daten sdata clk pd 0.1f 0.1f 0.1f 0.1f c3 c4 c2 c1 daten sdata clk gnd1 byp vcc pd vcc1 vcc2 out gnd2 gnd3 gnd4 gnd5 gnd12 vcc6 vin vin+ gnd11 vcc5 gnd10 vcc4 vcc3 out+ gnd9 gnd8 gnd7 gnd6 u1 ad8322tssop r6 0 r14 0 r13 dni r12 dni r19 dni r15 0 r16 0 r17 dni r18 0 r11 dni r10 0 r20 dni c16 dni c9 dni wht figure 13. evaluation board schematic obsolete
rev. 0 ad8322 C15C evaluation board bill of materials ad8322 evaluation board rev. dc single-ended inverting input revised june 22, 2000 qty. description vendor ref desc. 1 10 f 16 v. c size tantalum chip capacitor ads# 4-7-6 c18 12 0.1 f 50 v. 1206 size ceramic chip capacitor ads# 4-5-18 c1 8, 10 13 10 0 1/8 w. 1206 size chip resistor ads# 3-18-88 r1, 2, 3, 6, 8, 10, 14 16, 18 1 118 1% 1/8 w. 1206 size chip resistor ads# 3-18-106 r7 8 white test point (clk, pd , cp, sdata, daten ) ads# 12-18-42 tp1 6, 17, 19 1 black test point (gnd) ads# 12-18-44 tp20 1 red test point (vcc) ads# 12-18-43 tp15 2 yellow test point (+/- input) ads# 12-18-32 tp13 & tp14 475 right-angle bnc telegartner # j01003a1949 ads# 12-6-28 s1 4 (input, output) 1 centronics type 36-pin right-angle female connector ads# 12-3-50 p1 2 5-way metal binding post ads# 12-7-7 j1, 2 (vcc, gnd) 1 toko # 617 db-a0070 transformer toko # 617db-a0070 t2b 1 diplexer pulse * pulse u2 1 ad8322 (tssop) ads# ad8322 d.u.t. (u1) 1 ad8322 rev. e evaluation pc board d.s.c. evaluation pc board 4#4 40 1/4 inch ss panhead machine screw ads# 30-1-1 4#4 40 3/4 inch long aluminum round stand-off ads# 30-16-3 2# 2 56 3/8 inch ss panhead machine screw ads# 30-1-17 (p1 hardware) 2 # 2 steel flat washer ads# 30-6-6 (p1 hardware) 2 # 2 steel internal tooth lockwasher ads# 30-5-2 (p1 hardware) 2 # 2 ss hex. machine nut ads# 30-7-6 (p1 hardware) do not install c9, c14 c16, tp7 tp12, tp21, tp22, r4, r5, r9, r11 r13, r17, r19, r20, t1, t2a. * pulse diplexer part # s b5008 (42 mhz), cx6002 (42 mhz), b5009 (65 mhz). obsolete
rev. 0 C16C c02049C2.5C7/00 (rev. 0) printed in u.s.a. ad8322 28-lead tssop (ru-28) 0.177 (4.50) 0.169 (4.30) 28 15 14 1 0.386 (9.80) 0.378 (9.60) 0.256 (6.50) 0.246 (6.25) pin 1 seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0 outline dimensions dimensions shown in inches and (mm). obsolete

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